integrated circuit systems, inc. general description features ics9158-05 block diagram 9158-05 rev b 05 / 08 / 97 applications the ics9158-05 is a low cost frequency generator designed specifically to clock pentium systems using the triton chip set. three copies of the cpu clock are available at 50, 60, or 66.7 mhz. five copies of the synchronous bus clock run at half the cpu frequency. a 14.318 mhz refclk, 12 mhz, keybd, and 24 mhz floppy clock are also provided. each high drive output is capable of driving a 30pf load with better than 1v/ns typical slew and have a duty cycle of 505%. the synchronous outputs are skew controlled to within 250ps and cpu clocks lead bus clocks by 2-5ns. glitch-free start and stop of the cpu and bus clocks is provided as well as a power-down mode with all clocks forced low and the internal oscillators and plls powered-down. power-up time is less than 10ns. all frequency transitions are gradual and meet the intel cycle-to-cycle timing specification for 486 and pentium microprocessors. ? 3 cpu and 5 synchronous bus clocks ? 50/60/66 mhz and glitch-free stop clock selections ? 250ps skew between all synchronous outputs ? outputs drive up to 30pf load with 1v/ns slew ? 2-5ns early cpu clocks support triton chip set ? compatible with 486 and pentium cpus ? consumes less than 10a in power-down mode ? on-chip loop filter components ? 3.0v - 5.5v supply range ? 24-pin soic package ? ideal for risc or cisc systems such as 486, pentium, powerpc,? etc. requiring multiple cpu and synchronous bus clocks. buffered clock generator for pentium ? /triton ? systems advanced information pentium and triton are trademarks of intel corporation. powerpc is a trademark of motorola corporation advance information documents contain information on new products in the sampling or preproduction phase of devel- opment. characteristic data and other specifications are subject to change without notice.
2 ics9158-05 advanced information pin configuration pin descriptions for ics9158-05 24-pin soic * input pin has internal pull-up to vdd. functionality vdd = +5v10%, ta=0c to 70c unless otherwise stated pd# forces all outputs low and powers-down the oscillator and pll circuitry, minimizing power consumption. in order to ensure glitch-free start and stop of the cpu and bus clocks, pd# should be asserted after the cpu and bus clocks have stopped, and be deasserted 10ms (maximum pll lock time) prior to starting the clocks. oe pd# floppy (mhz) keybd (mhz) 1 1 24 12 1 0 low low 0 x tristate tristate pin number pin name type description 1 refclk out 14.318 clock output. 2 x2 out crystal connection, which includes output crystal load capacitance. 3x1 in crystal connection, which includes crystal load capacitance and feedback bias for a nominal 14.31818 mhz parallel-resonance 12pf crystal. 4 vdd pwr digital power supply. 5 gnd pwr digital ground. 6 keybd out 12 mhz keyboard clock output. 7 floppy out 24 mhz floppy disk clock output. 8 bus0 out bus clock output. 9 agnd pwr analog ground. 10 oe in output enable. tristates all outputs when low.* 11 bus1 out bus clock output. 12 gnd pwr digital ground. 13 cpu0 out cpu clock output. 14 cpu1 out cpu clock output. 15 pd# in power-down input shuts off both pll stages when low.* 16 avdd pwr analog power supply. 17 bus2 out cpu clock output. 18 bus3 out bus clock output. 19 gnd pwr digital ground. 20 vdd pwr digital power supply. 21 cpu2 out cpu clock output. 22 bus4 out bus clock output. 23 fs1 in clock frequency select #1.* 24 fs0 in clock frequency select #0.* oe pd# fs1 fs0 cpu ratio x1,x2, ref (mhz) cpu (0:2) (mhz) bus (0:4) (mhz) 1 1 0 0 14/4xx1 14.318 50 25 1 1 0 1 14/3xx1 14.318 66.7 33.3 1 1 1 0 42/10xx1 14.318 60 30 1 1 1 1 (stop) 14.318 low low 10xx (pwr down) low *low *low 0 x x x - tristate tristate tristate
3 ics9158-05 advanced information electrical characteristics at 5v absolute maximum ratings avdd, vdd referenced to gnd . . . . . . . . . . . . . . . . 7v operating temperature under bias. . . . . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +150c voltage on i/o pins referenced to gnd. . . . . . . . . . . gnd -0.5v to vdd +0.5v power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 watts stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il 0.8 v input high voltage v ih 2.0 v input low current i il v in =0v (pull-up) -20 a input high current i ih v in =v dd -5 5 a output low voltage v ol i ol =20.0ma 0.25 0.4 v output high voltage 1 v oh i oh =-30ma 2.4 3.5 v output low current 1 i ol v ol =0.8v 45 65 ma output high current 1 i oh v oh =2.0v -55 -35 ma supply current i dd no load, 66 mhz 67 100 ma output frequency change over supply and temperature 1 f d with respect to typical frequency 0.002 0.01 % short circuit current 1 i sc each output clock 25 56 ma pull-up resistor value 1 r pu input pin 680 k w input capacitance 1 c i except x1, x2 8 pf load capacitance 1 c l pins x1, x2 20 pf v dd = +5v10%, t a =0c to 70c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production.
4 ics9158-05 advanced information electrical characteristics ( continued ) note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units output rise time, 0.8 to 2.0v (note 1) t r 30pf load - 1 1.5 ns rise time, 20% to 80% v dd (note 1) t r 30pf load - 2.5 3 ns output fall time, 2.0 to 0.8v 1 t f 30pf load - 0.5 1.5 ns fall time, 80% to 20% v dd 1 t f 30pf load - 1.5 2 ns duty cycle 1 d t 30pf load 45/55 48/52 55/45 % jitter, one sigma 1 t j1s as compared with clock period 0.5 2.0 % jitter, absolute t jab -5 2 5 % jitter, absolute t jab 25-66mhz clocks -250 250 ps input frequency f i 14.318 mhz clock skew between cpu and 2xcpu outputs t sk 100 250 ps frequency transition time 1 t ft from 4 to 50 mhz 13 20 ms v dd = +5v10%, t a =0c to 70c unless otherwise stated
5 ics9158-05 advanced information v dd = +3.3v10%, t a =0c to 70c unless otherwise stated electrical characteristics at 3.3v note 1: parameter is guaranteed by design and characterization. not 100% tested in production. dc characteristics parameter symbol test conditions min typ max units input low voltage v il 0.8 v input high voltage v ih 2.0 v input low current i il v in =0v(pull-up) -10 a input high current i ih v in =v dd -5 a output low voltage v ol i ol =10ma 0.1v dd v output high voltage 1 v oh i oh =-5ma 0.85v dd v output low current 1 i ol v ol =0.2v dd 20 30 ma output high current 1 i oh v oh =0.7v dd -15 -10 ma supply current i dd no load, 66 mhz 43 65 ma output frequency change over supply and temperature 1 f d with respect to typical frequency 0.002 0.01 % short circuit current 1 i sc each output clock 25 56 ma pull-up resistor value 1 r pu input pin 900 k w input capacitance 1 c i except x1, x2 8 pf load capacitance 1 c l pins x1, x2 20 pf ac characteristics parameter symbol test conditions min typ max units output rise time, 0.8 to 2.0v 1 t r 30pf load - 1 3.0 ns rise time, 20% to 80% v dd 1 t r 30pf load - 2.5 4.0 ns output fall time, 2.0 to 0.8v 1 t f 30pf load - 0.5 2.5 ns fall time, 80% to 20% v dd 1 t f 30pf load - 1.5 4.0 ns duty cycle 1 d t 30pf load 40/50 44/46 50/40 % jitter, one sigma 1 t j1s as compared with clock period 0.5 2.0 % jitter, absolute 1 t jab 25% jitter, absolute 1 t jab 25-66 mhz clocks 300 ps input frequency f i 14.318 mhz clock skew window between cpu and 2xcpu outputs 1 t sk 100 250 ps frequency transition time 1 t ft from 4 to 50 mhz 13 20 ms
6 ics9158-05 advanced information frequency transitions a key feature of the ics9158-05 is its ability to provide smooth, glitch-free frequency transitions on the cpu and bus clocks when the frequency select pins are changed. the frequency transition rate does not violate the intel 486 or pentium specification of less than 0.1% frequency change per clock period. ics9158-05 cpu clock decoding table (using 14.318 mhz input. all frequencies in mhz) vdd=5v10% or 3.3v10%, temp=0-70c pd# forces all outputs low and powers-down the oscillator and pll circuitry, minimizing power consumption. in order to ensure glitch-free start and stop of the cpu and bus clocks, pd# should be asserted after the cpu and bus clocks have stopped, and be deasserted 10ms (maximum pll lock time) prior to starting the clocks. using an input clock as a reference the ics9158-05 is designed to accept a 14.318 mhz crystal as the input reference. with some external changes, it is possi-ble to use a crystal oscillator or other clock sources. please see application note aan04 for details on driving the ics9158-05 with a clock. oe pd# fs1 fs0 cpu ratio x1,x2, ref (mhz) cpu (0:2) (mhz) bus (0:4) (mhz) 1100 14/4xx1 14.318 50 25 1101 14/3xx1 14.318 66.7 33.3 1110 42/10xx1 14.318 60 30 1111 (stop) 14.318 low low 10xx (pwr down) low *low *low 0 x x x - tristate tristate tristate oe pd# floppy (mhz) keybd (mhz) 1 1 24 12 1 0 low low 0 x tristate tristate
7 ics9158-05 advanced information ordering information ics9158-05m example: ics xxxx-ppp m package type m=soic pattern number (2 or 3 digit number for parts with rom code patterns) device type (consists of 3 or 4 digit numbers) prefix ics, av=standard device; gsp=genlock device 24 lead soic lead count 24l dimension l 0.604 advance information documents contain information on new products in the sampling or preproduction phase of devel- opment. characteristic data and other specifications are subject to change without notice.
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